Field-effect transistors (FETs) and other related insulated-gate electronic devices are mainstay components of MOS integrated circuits. A MOSFET generally consists of two closely spaced, doped regions in a substrate--the source and the drain. The region between the two is the channel above which a thin insulation layer is formed. A gate electrode is formed directly over and completely covering the insulation layer directly above the channel and a voltage applied to the gate affects the electronic properties of the channel region, whereby the MOSFET is turned on and off.
The abbreviation MOS (metal oxide semiconductor) has become somewhat of a misnomer because for many applications the gate is formed of a polysilicon material which is doped to render it conductive. One problem that is encountered as ultra-shallow junction depths are pursued to reduce transistor sizing stems from the poly gate thickness not being scaled down at the same rate as the source/drain regions. Consequently, this scaling discrepancy leads to poly-depletion. As is commonly understood by those skilled in the art, poly depletion occurs when an anneal subsequent to the doping of the poly gate 18 is insufficient to drive the implanted impurities down the entire depth of the poly gate 18 as illustrated in prior art FIG. 1. Consequently, a portion 20 of the poly gate 18 nearest a gate oxide 22 is depleted of impurities and behaves as an insulating region. As a result, the transistor behaves as though the gate oxide 22 is substantially thicker, thereby resulting in a substantial degradation of device performance or even rendering the device inoperable. Increasing the implant energy or subsequent anneal time to remedy the poly depletion created another problem; namely it causes the shallow source/drain regions 24 and 26 to increase in depth. Consequently, a process designer faces a performance trade-off between reduced poly depletion and shallow source/drain junctions.
Another problem associated with the simultaneous processing of the gate with the source and drain regions involves the use of laser annealing. Laser annealing is a process by which a laser beam is radiated onto a wafer in a pulsed mode to anneal various semiconductor regions. Unfortunately, the laser energy required to melt (and thereby activate) the source/drain regions is higher than the energy needed to melt the polysilicon gate; therefore the energy required to form the source/drain regions causes excessive melting of the polysilicon gate which results in degraded oxide quality and, in some cases, poly gate destruction.
One prior art solution to the above problem involves the addition of an amorphizing implant such as silicon or germanium to reduce the melting temperature of the poly gate 18 and source/drains 24 and 26. The goal of this process was to stay below the melting temperature of the polycrystalline, but above the melting temperature of the amorphized region which allowed for melting of the poly gate 18 and the source/drain regions 24 and 26 without melting through the entire thickness of the poly gate 18. Unfortunately, this prior art process solution adds process steps and causes increased defects, thereby resulting in increased leakage and enhanced diffusion.
Accordingly, there is a need in the art for the elimination of poly depletion without negatively impacting the formation of shallow source/drain regions.